
Name :
kpan
Subtitle :
Verilog / VHDL Designer, Scientific Research Researcher & PCB Layout Designer
Location :
Paris, France
Number projects :
0
Rate currency :
$
Service :
Skill :
Kpan from Paris, France is interested in Verilog / VHDL Designer, Scientific Research Researcher & PCB Layout Designer. Kpan is working as a Freelancer and can be found in many freelancing marketplace. Kpan provides freelancing service
Engineering & Science. Kpan very Skilled with
Electronics, Microcontroller, PCB Layout and Scientific Research.
Kpan so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Kpan hourly rate is $100.00 USD and gets paid in $.
Please follow this link to hire directly.
Kpan so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Kpan hourly rate is $100.00 USD and gets paid in $.
Please follow this link to hire directly.
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