Name :
sikariar
Subtitle :
Verilog / VHDL Designer, Proofreading Proofreader & Matlab & Mathematica Engineers
Location :
Ranchi, India
Number projects :
0
Rate currency :
$
Skill :
Sikariar from Ranchi, India is interested in Verilog / VHDL Designer, Proofreading Proofreader & Matlab & Mathematica Engineers. Sikariar is working as a Freelancer and can be found in many freelancing marketplace. Sikariar provides freelancing service
Writing & Content, Websites, IT & Software, Engineering & Science, Data Entry & Admin and Design, Media & Architecture. Sikariar very Skilled with
Academic Writing, C++ Programming, Copy Typing, Editing, Electronics, Engineering, Excel, Mathematics, Proofreading, Video Upload, Web Search, Word and YouTube.
Sikariar so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Sikariar hourly rate is Ask for Hourly Rate and gets paid in $.
Please follow this link to hire directly.
Sikariar so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Sikariar hourly rate is Ask for Hourly Rate and gets paid in $.
Please follow this link to hire directly.
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