Name :
			
		
			 strawberrytd 
 
			
  			Subtitle :
			
  		
			 Research Analyst, Scientific Research Researcher & Verilog / VHDL Designer
			
  			Location :
			
		
  			
			 Des Moines,  United States
				
			Number projects :
			
		
		
			 0
			
			Rate currency :
			
		
		
	
		 $
			
		Service :
		
		
		
		
				Skill :
				
			
		
		Strawberrytd from Des Moines,  United States is interested in Research Analyst, Scientific Research Researcher & Verilog / VHDL Designer. Strawberrytd is working as a Freelancer and can be found in many freelancing marketplace.  Strawberrytd provides freelancing service 
		Engineering & Science,		Writing & Content,		Websites, IT & Software and		Data Entry & Admin. Strawberrytd very Skilled with 
		Scientific Research,		Research,		Powerpoint,		Perl,		Excel,		Electronics and		Data Entry.
		
Strawberrytd so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Strawberrytd hourly rate is $10.00 USD and gets paid in $.
Please follow this link to hire directly.
		Strawberrytd so far completed 0 projects and has about 0 reviews from clients who has used earlier freelancing projects. Strawberrytd hourly rate is $10.00 USD and gets paid in $.
Please follow this link to hire directly.
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